2.5D/3D IC Forum

 

Date: Wednesday, 8 May 2013
Time: 09:30 - 17:30
Venue: TECH West Stage


 

Morning Session

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Afternoon Session

 

Brought to you by:

 

Exclusively Sponsored by: 

 

 

Morning Session Chair:

Mr. Sesh Ramaswami, Managing Director, TSV and Advanced Packaging, Applied Materials, Inc.

 

Afternoon Session Chair:

Dr. Surya Bhattacharya, Director, Industry Development, Si Interposer (TSI) Program, Institute of Microelectronics

 

Morning Session Outline:

Theme: Wafer-Level Packaging for 2.5/3D Poised for Production: Controlling Variations

 

Advanced wafer-level packaging unit processes and integration schemes have been refined and optimized over the past several years.  Some techniques are now used in niche applications; through-silicon via technology has demonstrated readiness for full-scale production.  This program presents an overview of the production-readiness of 2.5 and 3 D approaches, complemented by perspectives on implementation from an OSAT production line.

 

Afternoon Session Outline:

Theme: Road to Volume Production of 2.5D/3D ICs

 

Over the past few years, advances in Silicon fabrication, assembly, packaging technologies coupled with improvements in EDA design capabilities have made the realization of 2.5D, 3DICs possible.  Companies in both logic, memory, and imaging space have released products using 2.5D, 3D IC technology.  Most companies are including 2.5D/3DIC as part of technology exploration space while developing new products.  The next phase of this evolution is the path to volume manufacturing.  This is the focus of this year’s 2.5D/3D IC forum.  As has been accepted across the industry, a collaborative approach is necessary for the industry to successfully drive up the demand and manufacturing volumes for 2.5D/3D ICs.  To better understand challenges that are encountered and anticipated in high volume manufacturing, we have included experts from fabless, IDM, EDA, Foundry, OSAT, Equipment, Materials companies.

 

Agenda

Morning Session

 

09:30 - 09:40


 

Welcome / Introductions / Overview

Mr. Sesh Ramaswami, Managing Director, TSV and Advanced Packaging

Applied Materials, Inc.


 

09:40 – 10:00


 

2.5/3D Front, Middle and Back-End Integration between Foundry and OSAT

Dr. Keh-Ching Huang, Corporate Marketing Director

United Microelectronics Corporation (UMC)


 

10:00 – 10:20

 

Advances in Wafer Bonding Technologies

Mr. Stefan Lutter, Product Manager Bonder

SUSS MicroTec Lithography GmbH


10:20 – 10:40

 

Process Development for TSV Metallization

Dr. Harold Philipsen, Researcher

IMEC


 

10:40 – 11:00


Break

 

11:00 – 11:20

 

Opportunities and Challenges for Design and Manufacturing of 2.5D Heterogeneous Systems on Through Silicon Interposers (TSI)

Dr. Surya Bhattacharya, Director, Industry Development Through Silicon Interposer Program

Institute of Microelectronics (IME)


 

11:20 – 11:40


 

Advanced Packaging Integration Roadmap

Mr. KiWook Lee, Director

Amkor Technology, Inc.


 

11:40 – 12:00


 

Fabrication and Electrical Characterization of 5x50µm TSV for 3D Integration

Dr. C.H. Toh, Senior Manager for TSV & WLP

Applied Materials, Inc.



Afternoon Session

 

13:00 – 13:25

 

3D Chip Stack Applications for Gaming, Consumer Applications

Keynote: Mr. Toshiyuki Hiroi, SVP, Sony Computer Entertainment Inc.


 

13:25 – 13:50

 

3D Integration and Low Cost Stacking Technologies

Dr. John Y. Xie, Director, Packaging R&D, Altera Corporation


 

13:50 – 14:15

 

Testing of 2.5D/3D ICS

Mr Daniel Rishavy, Principal Product Marketing and Applications Manager, Tokyo Electron America (TEL)


 

14:15 – 14:40

 

2.5 and 3D Integration - A Foundry Perspective

Mr Rajesh Nair, VP of Technology and Development, GLOBALFOUNDRIES


 

14:40 – 15:05

 

TCAD Framework for 2.5D/3D

Mr Russell Lee, Technical Director, Mentor Asia Pac.


15:05 – 15:15

 

Break Time & Networking


 

15:15 – 15:40

Process Integration and Challenges in 2.5D and 3D TSV Assembly

Keynote:  Mr Lee Choon Heung, Senior VP, Amkor Technology


15:40 – 16:05

 

Integrated 3D Wafer Level Packaging Solutions for Mobile Applications

Dr. Yoon Seung Wook, Director, STATS ChipPAC Ltd.


16:05 – 16:30

 

Bonding Technology Update

Mr Markus Wimplinger, Corporate Technology Development & IP Director, EV Group (EVG)


16:30 – 16:55

 

Overcoming Productivity Challenges in 2.5/3D Packaging

Mr Shekar Krishnaswamy, Sr. Manager, Applied Materials, Inc.


 

 

 

 

 

16:55 – 17:30

Panel Discussion Topic:

2.5D and 3D: On the Way To HVM

 

Moderator:

Ms E. Jan Vardaman, President, TechSearch International

 

Panelists:

  1. 1. Mr Toshiyuki Hiroi, SVP, Sony Computer Entertainment Inc.
  2. 2. Dr John Xie, Director, Altera Corporation
  3. 3. Mr Lee Choon Heung, Sr, VP, Amkor
  4. 4. Dr Yoon Seung Wook, Director, STATS ChipPAC Ltd
  5. 5. Mr. David Butler, VP, Marketing, SPTS Technologies
  6. 6. Mr Sesh Ramaswami, Managing Director, Applied Materials, Inc.

 

* Programs are subject to change without prior notice.

 

  

Chair's Introduction:

 



Dr. Surya Bhattacharya, Director, Industry Development, Si Interposer (TSI) Program, Institute of Microelectronics

Dr. Surya Bhattacharya is Director, Industry Development, for IME's Through Si Interposer (TSI) Program.  Surya has over 20 years of experience ranging from 0.8micron to 28nanometer CMOS while working in the US semiconductor industry at both Fabless companies and Integrated Device Manufacturers(IDM).  He joined IME from Qualcomm CDMA Technologies, San Diego, California, a world leader in semiconductor chips for 3G and LTE mobile phone markets.  At Qualcomm, he served as Director of Foundry Engineering while he oversaw technology and manufacturing ramps across multiple foundries in Asia and around the world.  Prior to Qualcomm, he was a Principal Foundry Engineer at Broadcom Corporation, Irvine, California, driving CMOS development and manufacturing for Broadcom's networking and wireless products at Asian foundries.  He started his career at Rockwell Semiconductor Systems, Newport Beach, California, where he was Senior Manager for CMOS technology development for Rockwell's communication products.  Surya obtained his Bachelor of Technology degree in Electrical Eng from the Indian Institute of Technology Madras, India in 1987;  MS, and Ph.D Degree in Microelectronics from the University of Texas at Austin, Texas, USA in 1993. <Top>

  

  

Panel Discussion Moderator's Introduction:

   

Ms. E. Jan Vardaman,  President, TechSearch International, Inc.

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided analysis on technology and market trends in semiconductor packaging since 1987.  She is co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly.  She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China.  She is a member of IEEE CPMT, IMAPS, IPC,  MEPTEC, and SEMI.  She received the “Die Products Industry Achievement Award,” at the 14th Annual International KGD Packaging and Test Workshop in September 2007.  She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.  <Top>

 

 

Speakers' Introduction:
 

Dr. John Y. Xie, Diector, Packaging R&D, Altera Corporation

Dr. Xie leads the Packaging Technology Research and Development organization at Altera (San Jose, CA).  He has been with Altera for 14 years.  His responsibilities include advanced interconnect and packaging technology research and development, new product development and introduction, 2.5D/3DIC integration design and manufacturing enablement, strategic supply chain management and strategic customer early engagement.

Prior Altera, he was a technology development manager at Prolinx Labs Corporation (San Jose, CA).

Dr. Xie graduated from Department of Physics, Peking University, and holds a Ph.D. Degree in Physics from Institute of Physics, Chinese Academy of Sciences and Post Doctoral from Department of Physics, University of California at Berkeley and Lawrence Berkeley Laboratory.

Dr. Xie has 27 published patents and over 50 academic and technical publications. <Top>

 


Dan Rishavy, Principal Product Marketing and Applications Manager, Tokyo Electron America (TEL)

Dan is a principal product marketing and applications manager for Tokyo Electron America's Test Systems group. Dan holds a BSEE degree from the University of South Florida and is completing an MBA from West Texas A&M University. He has been working in the Semiconductor Test industry for 15 years.  He has held variety of roles in application support, product management and marketing throughout his career at Hewlett Packard, Agilent, Verigy and now TEL. <Top>

 

Mr Rajesh Nair, VP of Technology and Development, GLOBALFOUNDRIES 

Raj Nair is the Vice President for Technology Development at GLOBALFOUNDRIES Singapore.  The Singapore TD team develops embedded NVM, RF and Power Management solutions for a wide range of products and customers.  Raj has over 25 years of Operations and R&D experience in the semiconductor and advanced battery industries.  He has held executive positions at Johnson Controls, Maxim, Motorola and On Semiconductor.  At Johnson Controls he was the Vice President for Advanced Manufacturing and Quality and launched the world’s largest automotive Li ion battery plant in Holland, MI.  He is a pioneer in the development of Smartpower integrated circuit development.  Raj has an MSEE degree from NTU and an MS ChE from Syracuse U.  <Top>

 




Russell Lee, Technical Director, Mentor Asia Pac.

Russell Lee joined Mentor as Technical Director for PacRim region by bringing in over 16 years of experiences in semiconductor industry. Starting as an engineer, Lee took on various positions including FAE, TME, and technical Marketing Manager at Synopsys, as well as Magma Design Automation during his residence in US. He moved to China on 2005 and shift his career focus to sales and business development. Lee took on managerial positions in Global Unichip Corp., Brite Semiconductor and TSSi.

Russell Lee holds BS. EE degree from National Tsing-hua University in Taiwan,and MS. EE degree from University of Southern California. <Top>

 

Dr. Yoon Seung Wook, Director, STATS ChipPAC Ltd.

Dr.YOON is currently in charge of products & technology marketing of advanced technology in STATS CHIPPAC LTD.  His major interests are for wafer level products including TSV (Through Silicon Via) technology, eWLB/Fanout WLP, WLCSP, IPD and integrated 3D IC packaging.

Prior to joining STATS CHIPPAC LTD, He was deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 150 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. <Top>

 

Choon Heung Lee, Corporate Vice President, Head of Corp. Business & Technology, Amkor Technology

Biography:
-    July 2012 - present : Head of Corp Business&Technology (US)
-    Jan 2010 – present : CTO for RnD and Process/Equipment Engineering (Korea)
-    Feb 1996 – Dec 2009 : Team managers and Head of RnD
-    Aug 1986 – Jan 1993 : MS and PhD at Case Western Reserve University
-    Mar 1977 – Aug 1985 : BS and MS at Korea University, Marine Corp. <Top>

  

Markus Wimplinger, Corporate Technology Development & IP Director, EV Group (EVG)

Markus Wimplinger is the director of EV Group’s (EVG) business unit for technology development and intellectual property.  In this role, Markus oversees EV Group’s global process engineering team.  Additional responsibilities include the management of R&D partnerships and contracts with third-party organizations such as companies or government-related entities, as well as intellectual property affairs associated with EVG’s process technology development efforts and 3D integration-related projects.

Prior to his current role, Wimplinger held positions within EVG with increasing responsibilities.  Most recently, he was director of technology for EV Group North America.  He began his career with EVG as a project manager at the company’s headquarters in Austria in 2001 where he was focused on customer-specific projects.  Wimplinger’s past work includes involvement in design, development, process technology and many other aspects of capital equipment manufacturing both at EVG and at his former position at a capital equipment supplier for non-semiconductor related industries. <Top>

  

Shekar Krishnaswamy, Sr. Manager, Applied Materials, Inc. 

Shekar works as a senior Manager in the Applied Materials Automation Products Group (APG).  His responsibility is in marketing and pre-sales of Scheduling, Dispatch and Modeling products and services.  He has more than 24 years experience in semiconductor manufacturing including fab, assembly and test.  He had worked for IBM, AMD and Motorola prior to joining Applied Materials.  His current focus is in the application of leading edge automation solutions for post-fab operations namely advanced packaging, bump, assembly and test.

Shekar has a Masters degree in Industrial Engineering and Operations Research from the University of Massachusetts at Amherst, USA and a Bachelors degree in Mechanical Engineering from Anna University in Chennai, India. <Top>

  

Toshiyuki Hiroi, Senior Vice President, Sony Computer Entertainment Inc.

Toshiyuki Hiroi is Senior Vice President for semiconductor technology at Sony Computer Entertainment Inc (SCE).  He has been with SCE for 18 years, responsible for development of LSIs for PlayStation® 2,  PSP® (PlayStation® Portable), and PlayStation® 3.


Prior to joining SCE, Hiroi was with a startup company developing networking products.  Before that, he was with Corporate Research Laboratories and Information Systems Research Laboratory at Sony Corporation.


Hiroi received his BE degree in Electrical Engineering from University of Tokyo, and MS degree in Computer Science from State University of New York at Buffalo. <Top>

 

Panel Discussion

 David Butler, VP, Marketing, SPTS Technologies

 

 

Presentation Abstract:

 

3D Inegration and Low Cost Stacking Technologies

Dr. John Y. Xie, Diector, Packaging R&D, Altera Corporation


System bandwidth is the key driving force of continued semiconductor technology innovation.  2.5D integration’s technology feasibility and its advantage in signal latency and channel power reduction has made it the center of the industrial wide R&D effort.  Meanwhile, the concern of its manufacturing readiness and cost has promoted many new fronts in low cost stacking technology R&D.  Face-to-Face stacking and ultrahigh density organic interconnect technology development are among the leading efforts in the semiconductor packaging assembly industry.  This presentation will give the highlight of these developments. <Top>

 

2.5 and 3D Integration - A Foundry Perspective

Mr Rajesh Nair, VP of Technology and Development, GLOBALFOUNDRIES


Die stacking using 2.5 and 3D architectures provide significant benefits in terms of system performance and process complexity reduction.  GLOBALFOUNDRIES has adopted a collaborative model for development and manufacturing of these products.  Ease of adoption will require a partnership with customers, wafer foundries, OSAT’s and suppliers. We believe the collaborative eco-system approach will enable design and process standardization which will provide clarity to customers and suppliers and lead to faster adoption of these solutions.  Detailed characterization was done to create design rules that were robust for volume manufacturing and to have no impact on device performance.  Process issues encountered during development are presented.  The 2.5 and 3D technologies at GLOBALFOUNDRIES have passed reliability tests and are ready for production.   <Top>

 

Integrated 3D Wafer Level Packaging Solutions  for Mobile Applications 

Seung Wook Yoon, Director, STATS ChipPAC Ltd.

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging solution with many advantages in comparison to standard Ball Grid Array (BGA) packages. The market for portable and mobile data devices connected to a virtual cloud access point is exploding, and driving high speed connectivity and increased functional convergence as well as increased packaging complexity and sophistication. This is causing an unprecedented demand for a variety of wafer level packages, 3D System-in-Package (SiP) solutions. We expect to see more exciting interconnect technologies in wafer level packaging such as 3D Through Silicon Via (TSV), 2.5D interposers, eWLB (embedded Wafer Level Ball Grid Array) / FO (Fan-out)-WLP  and 2.5D/3D eWLB technology to meet these needs.

This paper discusses the recent advancements of 3D WLP technologies of eWLB / FO-WLP and TSV solutions.  It also highlights the recent achievement of various features of 3D interconnects and performance.  Besides, this paper also presents case studies of selected mobile device application.  There would be some discussions of business opportunity and new supply chain approaches in wafer level packaging including wafer level final testing. <Top>

 

Process Integration and Challenges in 2.5D and 3D TSV Assembly

Mr. ChoonHeung Lee, Corporate Vice President, Head of Corp. Business & Technology,Amkor Technology

Small productions in FPGA and Power amplifier applications show that the TSV technology is close to reality even though the supply chain of this technology is still in question. In my context, starting off TSV making in Si at the foundries, MEOL, BEOL and Assembly processes at the OSATs are passed through to be a product. In this talk the processes for MEOL, BEOL and Assembly will be outlined with the process challenges surfaced out. In addition, some issues related to infrastructure building including capacity will be discussed. <Top>

 

3D Chip Stack Applications for Gaming, Consumer Applications

Mr Toshiyuki Hiroi, Senior Vice President, Sony Computer Entertainment Inc.

Game consoles require huge bandwidth in the interconnect in order to support high-quality computer graphics, although the system cost needs to be minimized as low as possible.  3D chip stacking technology is one of the solutions to resolve those requirements, and actually micro-bump-bonded CoC was employed in serveral models of PlayStation® platforms, while TSV  technology has not been used yet though it has many advantages over micro-bump-bonded CoC. This presentation will discuss why TSV technology has not been used in PlayStation® <Top>

 

Overcoming Productivity Challenges in 2.5/3D Packaging 

Shekar Krishnaswamy, Sr. Manager, Applied Materials, Inc. 

 

Wafer level packaging and in particular 2.5/3D packaging is evolving into a major technological advancement with the potential application in the creation of tens of billions of device using these technologies.  While the performance and miniaturization aspects are quite promising, there are significant challenges in achieving competitive costs.  The main reason is the fabrication of such devices on fab-type equipment which are heavily capital intensive.  This contrasts significantly from traditional or legacy packaging technologies which are produced in relatively low capital assembly and test factories.   Most of the current efforts for cost reduction in 2.5/3D packaging seem to revolve around improvements in product design, materials and processes.  The key aspect of manufacturing and equipment productivity approaches for achieving cost efficiencies do not seem to be getting the attention it deserves.  Moreover, there seems to be significant influence exerted by the inertia of traditional and legacy packaging manufacturing.  These traditional methods will not help achieve the efficiencies required to achieve market success.

In silicon based 2.5/3D manufacturing, major differences exist in the many different forms.  These include unbalanced equipment arising from differences in batch sizes, raw process times, equipment reliability, need for peripheral equipment, higher non-value added steps like cleans, inspections and measurements, product handling and transport, etc.  Such factors significantly impact the ability to manufacture product continuously and in high volumes.  This paper will present the methods and approaches required at different points in the lifecycle of a silicon based 2.5/3D factory to achieve high volume and continuous flow manufacturing.  Concepts such as factory automation, operational modeling and simulation, product dispatching and scheduling will be discussed.  The critical aspect of successful implementation of such techniques in the factory floor will also be presented. <Top>